1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices and, more particularly, a method of manufacturing semiconductor devices including a step of exposing a resist by use of an exposure mask.
2. Description of the Prior Art
A film patterning step in terms of photolithography technique has been essentially required in order to manufacture semiconductor integrated circuits (LSIs). In a photolithography technique, the fine pattern of the LSIs obtained by a reduction-type projection printing method has been employed to enable fine patterning of the LSIs. In order to improve resolution in exposure process, an exposure light having a short wavelength such as i beam (365 nm) etc. and a projection lens system having a large numerical aperture (NA) have been adopted.
In the exposure process, by use of a reticle, as shown in FIG. 1A, having thereon an LSI pattern area 101 and a dicing line area 102 around the LSI pattern area 101, a plurality of LSI patterns 104 are exposed on a wafer 103 shown in FIG. 1B.
A depth of focus of the exposure apparatus can be made small by increasing the numerical aperture and shortening the wavelength of the exposure light. Therefore, an image point of the exposure light must be adjusted with high accuracy to a surface of a resist, as a material to be exposed, formed on the wafer 103.
An image plane of the stepper must be adjusted to be in focus over an entire area of the LSI circuit pattern (referred to also as an exposure area hereinafter). Such operations for a location adjustment is called as a level adjustment. The level adjustment must be effected before the first exposure process of the LSI pattern. In general, once the level adjustment has been done, it is not adjusted repeatedly in succeeding exposure processes.
The level adjustment is effected based on the following procedures (1) to (4).
(1) By changing an amount of slant of a stage on which the wafer is positioned, a plurality of LSI patterns having their different slant amounts are exposed on the resist formed on the wafer. Since image points of the LSI patterns are differentiated from each other by changing their slant amounts, both a just-focused exposure state and a defocused exposure state can be caused.
(2) After developing the resist, pattern shapes formed in the four corners of each exposure area are checked to detect an amount of change in focus. Thereby, an optimum focus value is determined.
(3) Based on optimum focus values on plural points, a relative amount of slant of the surface of the wafer can be determined.
(4) The amount of slant of the stage can be adjusted by inputting the determined relative amount of slant into the exposure apparatus. Thus, the exposure apparatus is set to an ordinary state capable of exposing.
However, suppose that the exposure apparatus is used for a long time after the above level adjustment is completed, the condition of the stage sometimes changes gradually or suddenly to thus cause the amount of slant of the stage to change. Therefore, after completing the development, it must be determined by judging the pattern shapes in the four corners of the exposure area whether the amount of slant is still proper or not.
But, since the LSI circuit patterns are not always formed as the same patterns in the four corners of the exposure area, it becomes difficult to determine which pattern shape is relatively proper or not. Besides, it is difficult to compare the patterns in the four corners of the exposure area with each other because of their discrete locations. Accordingly, that comparison is to be dependent on measurement. Thus, there is a drawback that the level adjustment operation becomes troublesome so that it takes a lot of time.
In addition, when adjusting the level of the stage, it depends on operator's experiences to judge whether the optimum focus has been obtained or not. Thus, there is a case where, because of the operator's poor experiences, non-optimum amount of slant of the stage is passed up. In such case, when the wafer is subject to the succeeding manufacturing steps, the defect of the LSI can be found at the time of the final LSI circuit test. Thereby, a drawback is caused that a yield of the LSI is lowered.